Categories: PCs and Hardware

Continued from The Bottom Line

Pipelining is a technique used by RISC and CISC microprocessors to break the execution of individual instructions into stages and overlap the stages so several instructions can be processed in parallel. Both 486 and Pentium CPUs use the five-stage pipeline diagrammed in Figure A. The values in the boxes represent instructions--I1 for instruction number 1, I2 for instruction number 2, and so on. The five stages of the pipeline are:

    *  PF, which fetches an instruction from the processor cache
       or memory;

    *  D1, which decodes the instruction;

    *  D2, which generates a memory address if the instruction
       includes a memory reference;

    *  EX, which executes the instruction; and

    *  WB, which stores, or "writes back," the result.

FIGURE A: Pipelining allows more than one microprocessor instruction to be serviced at once. Time moves from left to right in units of a clock cycle. Follow the first instruction, I1, from left to right, and you can see that other operations enter the pipeline before I1 is finished. This allows the microprocessor to average 1 clock cycle for each instruction.

Under ideal conditions, each stage requires 1 clock cycle. You can trace the path that a single instruction takes through the pipeline by following I1 from start to finish. During the first clock cycle, I1 is fetched. During the second clock cycle, it is decoded. I2, meanwhile, is being fetched. After 5 clock cycles, processing of I1 is complete. When the pipeline is fully loaded, an average of one instruction per clock cycle can be output from the pipeline, like cars rolling off an assembly line. The Pentium's superscalar design incorporating two independent pipelines nominally doubles the processor's instruction throughput.

 

Published as Tutor in the 10/24/95 issue of PC Magazine.