Categories: PCs and Hardware

Continued from RISC: The Myth

In reality, there's nothing RISC about a lot of RISC chips any more--that is, their instruction sets aren't really reduced. The first RISC computer was developed by IBM in the mid-seventies. Since that time, the number of transistors that chip manufacturers can pack onto a silicon wafer has steadily increased. A Pentium contains more than 3 million transistors in an area that is roughly a half-inch square (see Figure 1). The sheer number of transistors, combined with architectural improvements to the chip itself, allows a Pentium to execute two instructions per clock cycle.

The Pentium doesn't actually perform an instruction in half a clock cycle; many instructions still require multiple clocks. But a technique called pipelining allows instructions to be overlapped, so that five instructions each requiring 5 clock cycles can be completed in a total of 5 clocks--an average of one instruction per clock. (For more on pipelining, refer to the sidebar "Pipelining: How It Works.") And the Pentium's two independent execution units, which qualify the Pentium as a superscalar microprocessor, permit two pipelines to run in parallel.

So much for cutting out instructions to make the remaining ones faster. With today's transistor budgets (a chip designer's term for the number of transistors allotted for use), it seems that all chips average 1 clock or less per instruction, no matter how complex their instruction sets.

What really distinguishes RISC from CISC these days is more deeply rooted in the chip architectures. In their book Inside the PowerPC Revolution (1994, Coriolis Group), which presents a lucid analysis of RISC and the PowerPC architecture in particular, Jeff Duntemann and Ron Pronk point out several key traits that characterize today's RISC designs. Among them:

• RISC microprocessors have more general-purpose registers. The best way to write fast code is to maximize the number of operations performed "on-chip" and minimize the number of accesses to data stored in memory. More registers make this goal more attainable. Register accesses are nearly instantaneous; memory accesses take time. A Pentium has just eight general-purpose registers, but a PowerPC chip has 32.
• * RISC microprocessors use load/store architectures. CPU instructions that operate on data in memory--for example, integer add instructions that add x to y, where y is a value stored in memory--are among the most expensive in terms of clock cycles. In addition, the implementation of these instructions tends to require a disproportionate number of transistors. RISC designs minimize the number of instructions that access memory in favor of load/store architectures that require y to be loaded into a register before x is added, then "stored" back to memory.
• RISC microprocessors use uniform instruction lengths. On a Pentium, the length of one instruction can vary from as little as 1 byte to as many as 7 (more if 32-bit code is executed in a 16-bit segment). RISC designers, on the other hand, favor making all instructions the same length--usually 32 bits. This simplifies the instruction-fetching and decoding logic and also means an entire instruction can be retrieved with one 32-bit memory access.
• RISC microprocessors emphasize floating-point performance. Traditionally, the stronghold of RISC machines has been the scientific community, whose applications do more floating-point math than a typical word processor or spreadsheet. Therefore, RISC microprocessors nearly always have high-performance floating-point units built in. Only recently, with the Pentium, has an entire line of Intel chips included a math coprocessor (remember the 486SX?), and integer operations are still considered the Pentium's mainstay.

In general, RISC designers have been quick to adopt cutting-edge technologies such as on-chip code and data caches, superscalar designs, instruction pipelining, and branch prediction logic--anything to give their chips a performance boost. But Intel has incorporated the same technologies, so it's difficult to distinguish RISC from CISC on the basis of those features. There are some RISC chips that stay closer to the original intent of RISC. For example, Digital's Alpha and the MIPS RX000 family combine reduced instruction sets with huge internal caches and Olympian clock speeds of 200 MHz and higher.

Chip makers such as AMD, Cyrix, and NexGen are further blurring the line between CISC and RISC by incorporating RISC-like features into their Pentium clones. Internally, for example, NexGen's Nx586 and AMD's K5 use instructions that are all the same length--as does Intel's own impending P6 chip. The internal instruction sets employ load/store architectures that limit the number of instructions that perform memory accesses.

The NexGen and AMD chips also address the Pentium's limited register availability (which adversely affects the chip's ability to execute instructions concurrently in its two pipelines) by implementing 22 and 40 registers, respectively. So that existing software written for the x86 has access to all the registers, the chips use a sophisticated register renaming scheme to dynamically map the "visible" registers to other members of the register set. For more on register renaming, branch prediction, and other advances in the architecture of Pentium-class microprocessors, see "What's Next Inside?" and "Inside the Chips" in our issue of February 21, 1995.

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Published as Tutor in the 10/24/95 issue of PC Magazine.