Categories: PCs and Hardware

Continued from Introduction

The first time I heard the term RISC, it was explained to me like this: By reducing the number of instructions that a CPU supports and thereby reducing the complexity of the chip, it's possible to make individual instructions execute faster and achieve a net gain in performance even though more instructions might be required to accomplish a task.

Okay, I thought, sounds plausible. An instruction is a command encoded in 1s and 0s that makes a microprocessor do something. When a developer writes a program in C or C++ or some other high-level language, the compiler translates each statement into one or more microprocessor instructions. So that programmers who want to see these microprocessor instructions don't have to wallow in 1s and 0s, the instructions are represented with mnemonics--for example, mov, which moves a value from one location to another, and add, which adds two values together. The following statement adds two integer variables named b and c and then stores the result in a:

    a = b + c;

A C compiler might translate this statement into the following sequence of instructions:

    mov     ax,[VariableB]
    add     ax,[VariableC]
    mov     [VariableA],ax

The first instruction copies the contents of the memory location that holds the value of b into the microprocessor's AX register. (A register is a storage location inside the microprocessor that holds a small amount of data, usually 16 or 32 bits, just like a memory location. Because registers are a part of the microprocessor, register accesses are much faster than memory accesses.) The second instruction adds the value of c to the contents of AX, and the third copies the result, which is in AX, to the memory location where the a variable is stored. Any program, no matter how complex, ultimately translates into bite-size series of instructions like this one.

Modern application programs often contain hundreds of thousands of lines of code. Operating systems are even more complex: Microsoft Windows 95 contains about 10 million lines, most of it written in C, and Windows NT contains more than 5 million lines written in C and C++. Imagine translating a million lines of C code into a set of instructions from 1 to perhaps 20 or 30 instructions each, and it's easy to see why software today is so complicated--and so difficult to debug. But we digress.

When a program runs, the microprocessor reads, or fetches, the instructions one by one and executes them. It takes time to fetch an instruction and more time to decode that instruction to determine what the 1s and 0s represent. And once the instruction begins executing, it takes a certain number of clock cycles to run to completion. A clock cycle is one beat of the oscillator that drives the microprocessor. On a 25-MHz 386, 1 clock cycle (or simply clock) is equal to 40 billionths of a second, or 40 nanoseconds. For a 120-MHz Pentium, 1 clock is less than 9 nanoseconds. One way to make a microprocessor run software faster is to increase the clock speed. Another way is to decrease the number of clocks required to execute an instruction. Everything else being equal, a 100-MHz microprocessor will deliver only half the performance of a 50-MHz microprocessor if the former requires 4 clocks per instruction but the latter requires just 1. Traditionally, CISC microprocessors like the x86 have required anywhere from 1 to more than 100 clocks to complete an instruction. For example, the mul (multiply) instruction on the 8088 that powered the original IBM PC required up to 133 clocks to multiply two 16-bit integers. A register-to-register mov, by contrast, required only 2 clocks. The same multiply on a 486 requires as few as 13 clocks, and mov requires just 1. That's one reason you can't compare, say, a 25-MHz 386 with a 120-MHz Pentium based on clock speeds alone. The instruction timings are different, and with each successive generation of the x86, Intel has reduced the clock counts for individual instructions.

What does this have to do with RISC? Since the dawn of the microprocessor age, the holy grail for chip designers has been to develop a CPU that requires 1 clock cycle per instruction--not just certain instructions, but every instruction. Given an unlimited number of transistors to work with, a microprocessor can be made into a 1-clock-per-instruction device. But the transistors on a CPU have to fit into a limited amount of real estate, so transistor counts are limited. RISC's original goal was to limit the number of instructions on the chip so that each could be allocated enough transistors to make it execute in one clock cycle. Rather than provide a mul instruction, for example, the microprocessor's designers might make sure that add executes in one clock. Then a compiler could multiply a and b by adding a to itself b times or b to itself a times. A CISC CPU could multiply 5 by 10 like this:

    mov     ax,10
    mov     bx,5
    mul     bx

But a RISC chip might do it like this:

    mov     ax,0
    mov     bx,10
    mov     cx,5

Begin:

    add     ax,bx
    loop    Begin    ;loop cx times

This is admittedly a contrived example (modern RISC chips do have multiply instructions), but it's illustrative nonetheless. The RISC version uses more instructions, but if the instruction timings are low enough, the RISC chip might do in 20 clocks what the CISC chip requires 100 clocks to do. Given a finite number of transistors to work with, there's a trade-off between instruction-set complexity and instruction timing. RISC seeks to strike a better balance between the two to produce a faster microprocessor. The transistors a RISC chip saves on large instructions can be used for cache, pipelines (more about these in a moment), and more registers.

At least that's the theory. There's just one small problem: If you check the technical manuals, you'll find that today's RISC chips often have richer and more complex instruction sets than CISC chips. The PowerPC 601, for example, supports more instructions than the Pentium. Yet the 601 is considered a RISC chip, while the Pentium is definitely CISC. So what does RISC really mean? And what distinguishes a RISC chip like the PowerPC 601 from a CISC chip like the Pentium? Ironically, the answer has nothing to do with the size of the instruction set.

Continues...

Published as Tutor in the 10/24/95 issue of PC Magazine.